1. Field of the Invention
This invention relates to a semiconductor memory device having electrically rewritable and non-volatile memory cells.
2.Description of the Related Art
A NAND-type flash memory is known as one of electrically rewritable and non-volatile semiconductor memories (EEPROMs). Since this flash memory is formed of NAND cell units, each of which has plural memory cells connected in series in such a manner that adjacent two memory cells share a source/drain diffusion layer, it is possible to lessen a unit cell area of a memory cell array, thereby providing a memory with a large capacitance.
On the other hand, a NAND-type flash memory has a sense amplifier circuit (i.e., page buffer) with sense amplifiers for one page data, and data read and write are performed by a page of the memory cell array. One page data are serially transferred, for example, two-byte by two-byte (or byte by byte), between the sense amplifier circuit and external input/output terminals. With such the scheme, the NAND-type flash memory may be formed to have a substantially high rate read/write performance in spite of large capacitance thereof.
Further, the data output operation for one page read data in the sense amplifier circuit is done as a serial data transferring operation as synchronous with a read enable signal, which is a read-use reference clock externally supplied (refer to, for example, Unexamined Japanese Patent Application Publication No. 2003-233992).
However, in such a scheme that read data output operation is directly controlled by the read enable signal supplied from the external, it becomes difficult to provide a flash memory with a high-speed data read performance under the condition of a more lowered voltage. The reason is as follows. In case the read enable signal supplied to the flash memory is declined in change rate, and duty ratio thereof is changed due to noises on the external bus line, load variations of the bus line, impedance mismatching between the driver of an external controller and load thereof including the bus line, and the like, it becomes difficult to do timing control of the read data output operation. In detail, it may become impossible to secure a time period necessary for setting up data on the data output path disposed between the sense amplifier circuit and the input/output ports. This causes the flash memory to read erroneous data and/or data with erroneous addresses.